Size reduction of the semiconductor structures has provided significant improvement in the speed, performance, circuit density, and cost per unit function of semiconductor chips over the past few decades. As the density of semiconductor devices increases and the size of circuit elements becomes smaller, however, the resistance capacitance (RC) delay time increasingly dominates the circuit performance. To reduce the RC delay, there is a desire to switch from conventional dielectrics to low-k dielectrics for intermetal dielectrics, IMDs, and interlayer dielectrics, ILDs.
One example of low-k dielectrics are porous dielectrics such as the commercially available Dow Chemical's porous SILK product and JSR Corporation's JSR 5109. The dielectric constant of the porous material is a combination of the dielectric constant of the trapped gas, typically air, and the dielectric constant of the matrix material. Such materials may have pores as small as 5-10 nm and may achieve dielectric constants below about 3 or about 2.
Porous dielectrics present problems during processing, however. When there is an open surface pore, processing fluids can enter the dielectric and cause corrosion, mechanical damage, or increase the dielectric constant. Pore damage may also cause a surface that is preferably hydrophobic to become hydrophilic thereby causing absorption of moisture. It has also been observed that this degraded low-k dielectric material is more vulnerable to chemical attack during exposure to wet chemical cleanups.
Special pore damage problems arise with damascene interconnect formation. Damascene interconnect structures typically include copper as the interconnect conductor. Because of its high diffusivity and its tendency to act as a recombination center in silicon, steps must be taken to ensure that all the copper is confined to the damascene structure. This is conventionally accomplished with a barrier layer that lines the walls of the damascene interconnect trench and via. One problem is that a heavily damaged porous surface requires a thicker barrier layer to ensure that there are no thin patches through which copper could move. The thicker barrier layer, in turn, partially offsets the advantage of the low-k dielectric by increasing the resistance capacitance (RC) delay time.
In view of these and other problems, there is a need in semiconductor device manufacturing for methods to repair damaged porous dielectrics.